In a digital computer, the execution by the central processing unit of an instruction of a machine language program is implemented in part by the execution, under control of a microprogram, of sequences of micro-instructions which are stored in one or more memories. These memories are provided for internal machine use only and are not generally available for use by the computer system user or programmer, either for data or code storage.
Micro-instructions use the basic subcommands of the machine such as single add, shift or delete type commands. Typically a specific series of micro-instructions is required to carry out a single specific machine language instruction (such as a multiply instruction) which appears in the object code (or machine language program of a computer user.
The micro-instructions thus stored in memory are ordinarily divided into functional blocks or sequences, each of which performs a particular processing operation. However, due to the use of similar processing operations by more than one sequence, certain common micro-instruction sub-sequences may appear in two or more sequences. It would therefore be advantageous to eliminate the duplication of these common sub-sequences in order to save a certain number of memory positions.
To this end, it has been proposed to insert in the microprogram, at the point where a common sub-sequence is needed a sub-sequence initiating signal (sub-sequence call) and to add to the end of the sub-sequence an end-of-sub-sequence signal which retures to the normal order of microprogram execution. The instruction calling the Sub-microprogrm call stores the memory address following its own address (i.e., the return address) in a special register. This is depicted in FIG. 1, wherein is shown a microprogram calling instruction A, which calls the sub-sequence K-X, and the end-of-sub-sequence signal at X which signal returns control to the microprogram at return address B. At the end of the sub-sequence, the end-of-sub-sequence signal returns control to the address contained in this register (i.e., the return address).
It should be noted that various sub-sequences can be formed by varying the starting address of the sub-sequence as indicated by the sub-sequence calling instruction. FIG. 2 depicts such an arrangement wherein sub-sequence A contains micro-instructions d-1, while sub-sequence B contains micro-instructions g-1. However, since the end of the sub-sequence d-1 is defined by an end-of-sub-sequence signal at location 1, it is impossible with prior art arrangements to form a sub-sequence starting at g, for example, which terminates at a location other than 1. In other words, providing a return address signal at the end of each sub-sequence in essence closes the sub-sequences at that point where the return address signal occurs.